The present invention relates generally to the fabrication of semiconductor devices and nanoscale structures. More specifically, the present invention relates to a fabrication process which enables the fabrication of nanometer-scale structures having localized features difficult to create using conventional fabrication techniques.
The thrust of semiconductor fabrication over the past 40 years has been to smaller and more densely integrated devices. New manufacturing facilities currently are based on a feature size of 250 nanometers (250 nm), and the next generation will use a feature size approaching 180 nm. More recently, the challenge of fabricating practical quantum transport devices has driven development of special techniques, such a e-beam lithography, which can be used to routinely create device structures having features as small as 10 nm.
Semiconductor devices and quantum transport devices generally comprise a number of discrete material layers. These layers can be made from metals, insulators, or various types of semiconductors. They are often doped with impurities to tailor their electronic properties, and may be fabricated with a built-in strain to alter the bulk band structure. The thickness of these layers is usually significantly less than the minimum feature size.
A major force driving the development of smaller devices, and in particular of quantum transport devices, is the need for devices with faster response times. Devices with intrinsic response times in the sub-picosecond range can be designed based on resonant tunneling effects. Tunneling is an inherently fast physical process. In addition, devices based upon resonant tunneling often exhibit negative differential resistance. This property can be used to make oscillators and switching elements--in fact, most analog and digital circuitry, as well as optoelectronics, can be designed around such devices, resulting in a complete quantum electronics with peak operating frequencies in the millimeter to far-IR range.
Even if such devices are available, however, many potential difficulties appear in incorporation into practical applications. One example is that the parasitic capacitance and inductance associated with interconnects between devices and with electrical contacts to devices can limit the practical operating speed of a circuit comprising extremely fast devices. One such design restriction is that a conductor having a large cross-section is required to move electrons quickly from one point to another, e.g., to inform a second device that a first device has changed state. As suggested above, however, contacts and conductors with large cross-sections are often incompatible with the extremely thin material layers which typically appear in the desired device structures.
In the prior art, this dissonance causes a tradeoff between the desire to have speedy devices and the desire to allow speedy communication between devices, resulting in a compromise situation where the devices are slower than they might be in order to enable sufficiently fast interconnects to be made.
The above is just one example of a class of tradeoffs in microelectronic circuit design which are driven by the inability to reliably deposit continuous thin layers over localized thick obstacles. There is a long-acknowledged need for practical design and fabrication techniques to avoid such tradeoffs.
It is possible in principle to redesign suitable devices to combine a stack of flat thin layers with contacts and control structures having large cross-sections, simply by placing the contacts and control structures external to the sandwich of layers making up the basic device structure. To produce such designs with conventional fabrication methods, however, requires creation of large-scale buried localized structures. Such structures are difficult to replanarize prior to deposition of the thin device layers using conventional microelectronic fabrication techniques. There is thus a need for a new class of microelectronic fabrication techniques which allows the use of large-scale buried localized structures.
The present invention addresses the above need by allowing large-scale structures to be grown on a stop etch layer atop a substrate, followed by burying the features in an epoxy bond deployed between the device layers and a host substrate. The original substrate is then etched away, leaving a new free surface on the opposite side of the device layers on which large-scale contacts and the like can be grown. The present invention thus successfully combines large-scale (and hence fast) contacts and interconnects with flat thin device layers, thereby leading to faster overall circuit operation.